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Figure X7.27 in Software Printer Code39 in Software Figure X7.27




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Figure X7.27 using software todeploy code39 on asp.net web,windows application itf-14 7.28 Suppose Software Code-39 that a clocked synchronous state machine with the structure of Figure 7-35 is designed using D latches with active-high C inputs as storage elements. For proper next-state operation, what relationships must be satisfied among the following timing parameters tFmin, tFmax tCQmin, tCQmax tDQmin, tDQmax tsetup, thold tH, tL.

Minimum and m aximum propagation delay of the next-state logic. Minimum and maximum clock-to-output delay of a D latch. Minimum and maximum data-to-output delay of a D latch.

Setup and hold times of a D latch. Clock HIGH and LOW times..

7.29 Redesign Code-39 for None the state machine in Drill 7.9 using just three inverting gates NAND or NOR and no inverters.

7.30 Draw a state diagram for a clocked synchronous state machine with two inputs, INIT and X, and one Moore-type output Z. As long as INIT is asserted, Z is continuously 0.

Once INIT is negated, Z should remain 0 until X has been 0 for two successive ticks and 1 for two successive ticks, regardless of the order of occurrence. Then Z should go to 1 and remain 1 until INIT is asserted again. Your state diagram should be neatly drawn and planar (no crossed lines).

(Hint: No more than ten states are required). 7.31 Design a clocked synchronous state machine that checks a serial data line for even parity.

The circuit should have two inputs, SYNC and DATA, in addition to CLOCK, and one Moore-type output, ERROR. Devise a state/output table that does the job using just four states, and include a description of each state"s meaning in the table. Choose a 2-bit state assignment, write transition and excitation.

Copyright 1999 by John F. Wakerly Copying Prohibited Section 7.12 VHDL Sequential-Circuit Design Features equations, an d draw the logic diagram. Your circuit may use D flip-flops, J-K flipflops, or one of each. 7.

32 Design a clocked synchronous state machine with the state/output table shown in Table 7.32, using D flip-flops. Use two state variables, Q1 Q2, with the state assignment A = 00, B = 01, C = 11, D = 10.

. Ta b l e X 7 . 3 2 7.33 Repeat E xercise 7.32 using J-K flip-flops.

7.34 Write a new transition table and derive minimal-cost excitation and output equations for the state table in Table 7-6 using the simplest state assignment in Table 7-7 and D flip-flops. Compare the cost of your excitation and output logic (when realized with a two-level AND-OR circuit) with the circuit in Figure 7-54.

7.35 Repeat Exercise 7.34 using the almost one-hot state assignment in Table 7-7.

7.36 Suppose that the state machine in Figure 7-54 is to be built using 74LS74 D flipflops. What signals should be applied to the flip-flop preset and clear inputs 7.

37 Write new transition and excitation tables and derive minimal-cost excitation and output equations for the state table in Table 7-6 using the simplest state assignment in Table 7-7 and J-K flip-flops. Compare the cost of your excitation and output logic (when realized with a two-level AND-OR circuit) with the circuit in Figure 7-56. 7.

38 Repeat Exercise 7.37 using the almost one-hot state assignment in Table 7-7. 7.

39 Construct an application table similar to Table 7-10 for each of the following flipflop types: (a) S-R; (b) T with enable; (c) D with enable. Discuss the unique problem that you encounter when trying to make the most efficient use of don t-cares with one of these flip-flops. 7.

40 Construct a new excitation table and derive minimal-cost excitation and output equations for the state machine of Table 7-8 using T flip-flops with enable inputs (Figure 7-33). Compare the cost of your excitation and output logic (when realized with a two-level AND-OR circuit) with the circuit in Figure 7-54. 7.

41 Determine the full 8-state table of the circuit in Figure 7-54. Use the names U1, U2, and U3 for the unused states (001, 010, and 011). Draw a state diagram and explain the behavior of the unused states.

7.42 Repeat Exercise 7.41 for the circuit of Figure 7-56.

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