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5.fm Page 225 Friday, January 18, 2002 9:01 AM in .NET Develop European Article Number 13 in .NET 5.fm Page 225 Friday, January 18, 2002 9:01 AM




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chapter5.fm Page 225 Friday, January 18, 2002 9:01 AM use vs .net european article number 13 printer tobuild european article number 13 for .net Specific Terms for GS1 Barcodes Section 5.6 Perspective: Technology Scaling and its Impact on the Inverter Metrics S2. Figure 5.40 Evolu tion of power-density in micro- and DSP processors, as a function of the scaling factor S ([Sakurai97]). S is normalized to 1 for a 4 m process.

. Table 5.5 Scaling GTIN-13 for .NET scenarios for wire capacitance.

S and U represent the technology and voltage scaling parameters, respectively, while SL stands for the wire-length scaling factor. c represents the impact of fringing and inter-wire capacitances. Parameter Wire Capacitance Wire Delay Wire Energy Wire Delay / Intrinsic Delay Wire Energy / Intrinsic Energy Relation WL/t RonCint CintV2 General Scaling c/SL c/SL c/SLU2 cS/SL cS/SL.

The model predict s that the interconnect-caused delay (and energy) gain in importance with the scaling of technology. This impact is limited to an increase with c for short wires (S = SL), but it becomes increasingly more outspoken for medium-range and long wires (SL < S). These conclusions have been confirmed by a number of studies, an example of which is shown in Figure 5.

41. How the ratio of wire over intrinsic contributions will actually evolve is debatable, as it depends upon a wide range of independent parameters such as system architecture, design methodology, transistor sizing, and interconnect materials. The doom-day scenario that interconnect may cause CMOS performance to saturate in the very near future hence may be exaggerated.

Yet, it is clear to that increased attention to interconnect is an absolute necessity, and may change the way the next-generation circuits are designed and optimized (e.g. [Sylvester99]).

. chapter5.fm Page 226 Friday, January 18, 2002 9:01 AM THE CMOS INVERTER 5 . Figure 5.41 Evolu tion of wire delay / gate delay ratio with respect to technology (from [Fisher98])..

Summary This chap ean13+5 for .NET ter presented a rigorous and in-depth analysis of the static CMOS inverter. The key characteristics of the gate are summarized: The static CMOS inverter combines a pull-up PMOS section with a pull-down NMOS device.

The PMOS is normally made wider than the NMOS due to its inferior current-driving capabilities. The gate has an almost ideal voltage-transfer characteristic. The logic swing is equal to the supply voltage and is not a function of the transistor sizes.

The noise margins of a symmetrical inverter (where PMOS and NMOS transistor have equal currentdriving strength) approach VDD/2. The steady-state response is not affected by fanout. Its propagation delay is dominated by the time it takes to charge or discharge the load capacitor CL.

To a first order, it can be approximated as R eqn + R eqp t p = 0.69C L -------------------------- 2 Keeping the load capacitance small is the most effective means of implementing high-performance circuits. Transistor sizing may help to improve performance as long as the delay is dominated by the extrinsic (or load) capacitance of fanout and wiring.

The power dissipation is dominated by the dynamic power consumed in charging and discharging the load capacitor. It is given by P0 1 CLVDD2f. The dissipation is proportional to the activity in the network.

The dissipation due to the direct-path currents occurring during switching can be limited by careful tailoring of the signal. chapter5.fm Page 227 Friday, January 18, 2002 9:01 AM Section 5.8 To Probe Further slopes. The stati visual .net EAN-13 Supplement 2 c dissipation can usually be ignored but might become a major factor in the future as a result of subthreshold currents.

Scaling the technology is an effective means of reducing the area, propagation delay and power consumption of a gate. The impact is even more striking if the supply voltage is scaled simultaneously. The interconnect component is gradually taking a larger fraction of the delay and performance budget.

. To Probe Further The operation of the CMOS inverter has been the topic of numerous publications and textbooks. Virtually every book on digital design devotes a substantial number of pages to the analysis of the basic inverter gate. An extensive list of references was presented in 1.

Some references of particular interest that were explicitly quoted in this chapter are given below..
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