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B3 A3 B2 A2 B1 A1 B0 A0 use none none encoder tobuild none on .net data matrix Conditional Cell C 1 C 0 S1 S0 Data Capacity of QR Code Conditional Cell C 1 C 0 S1 S0 Conditional Cell C 1 C0 S 1 S 0 Conditional Cell C 1 C0 S 1 S 0 C out (a) Four-bit conditional-sum adder A B A B A A B S0 A A B B A B S1 A B A C0 A A A A B A A C1 A (b) Conditional adder cell Figure 0.4 Conditional-sum adder. [M, None, 1 1.3] Consider replacing all of the NMOS evaluate transistors in a dynamic Manchester carry chain with a single common pull-down as shown in Fgure 0.5.

a. Assume that each NMOS transistor has (W/L)N = 0.5/0.

25 and each PMOS has (W/L)P = 0.75/0.25.

Further assume that parasitic capacitances can be modeled by a 10 fF capacitor on each of the. Page 4 Friday, October 3, 2003 9:48 PM 11 Problem Set internal nodes: A, B, C, D, E, and F. Assume all transistors can be modeled as linear resistors with an on-resistance, Ron = 5 k . a.

Does this variation perform the same function as the original Manchester carry chain Explain why or why not. b. Assuming that all inputs are allowed only a single zero-to-one transition during evaluation, will this design involve charge-sharing difficulties Justify your answer.

c. Complete the waveforms in Figure 0.5b for P0 = P 1 = P2 = P3 = 2.

5 V and G0 = G1 = G2 = G3 = 0 V. Compute and indicate tpHL values for nodes A, E, and F. Compute and indicate when the 90% precharge levels are obtained.

. V DD P0 A none none B G0 G1 F P1 C G2 P2 D G3 P3 E 1 C in A E F 4 5 8 t(nsec). C in (a) Circuit schematic Figure 0.5 (b) Partial waveforms Alternative dynamic Manchester carry-chain adder. [M, None, 1 1.3] Consider the two implementations of Manchester carry gates in Figure 11-8. a.

Compare the delay per segment of the two implementations b. Compare the layout complexities of the two gates using stick diagrams. c.

In the precharged Manchester carry chain using the gate from b. find the probability that the carry signal is propagated from the 15th to the 16th bit of a 32-bit adder, assuming random inputs. [C, None, 11.

3] Consider the Radix-4 and Radix-2 Kogge-Stone adders from Figures 11-22 and 11-27 extended to 64-bits. All gates are implemented in domino and all gates in a stage have the same size. The adders have an overall fanout (electrical effort) of 6.

a. Using logical effort, identify the critical path. b.

Size the gates for minimum delay (hint: don"t forget to factor in branching). Which adder is faster c. Let"s now consider sparse versions of each of the above trees.

In a tree with a sparseness of 2, only every other carry is computed and it is used to select 2 sums. Similarly, a tree with a sparseness of 4 computes every fourth carry - and that carry signal is used to select 4 sums. Repeat a.

and b. for Radix-2 and Radix-4 trees with sparseness of 2 and 4 and compare their speed. Which adder is fastest d.

Compare the switching power of all adders analyzed in this problem. [C, None, 11.3] In this problem we will analyze a carry-lookahead adder proposed by H.

Ling more than 20 years ago, but still among the fastest adders available. In a conventional adder, in order to add two numbers A = an 12n 1 + an 22n 2 + ..

.. + a020 B = bn 12n 1 + bn 22n 2 + .


+ b020 we first compute the local carry generate and propagate terms:. Page 5 Friday, October 3, 2003 9:48 PM Digital Integrated Circuits - 2nd Ed gi = aibi p none none i = ai + bi then, with a ripple or a tree circuit we form the global carry-out terms resulting from the recurrence relation: Gi = gi + piGi 1 Finally, we form the sum of A and B using local expressions: S i = pi Gi 1 In the conventional adder, the terms Gi have, as described, a physical significance. However, an arbitrary function could be propagated, as long as sum terms could be derived. Ling"s approach is to replace Gi with: Hi = Gi + Gi 1 i.

e. Hi is true if "something happens at bit i" - there is a carry out or a carry in. Hi is so-called "Ling"s pseudo-carry".

a. Show that: Hi = gi + ti 1Hi 1 where pi = ai + bi (it was Ling s idea to change the notation). b.

Find a formula for computing the sum out of the operands and Ling"s pseudo-carry. c. Unroll the recursions for Gi and Hi for i = 3.

You should get the expressions fpr G3 and H3 as a function of the bits of input operands. Simplify the expressions as much as possible. d.

Implement the two functions using n-type dynamic gates. Draw the two gates and size the transistors. Which one helps us build a faster adder Explain your answer.

[M, None, 11.4] An array multiplier consists of rows of adders, each producing partial sums that are subsequently fed to the next adder row. In this problem, we consider the effects of pipelining such a multiplier by inserting registers between the adder rows.

a. Redraw Figure 11-31 by inserting word-level pipeline registers as required to achieve maximal benefit to throughput for the 4x4 multiplier. Hint: you must use additional registers to keep the input bits synchronized to the appropriate partial sums.

b. Repeat for a carry-save, as opposed to ripple-carry, architecture. c.

For each of the two multiplier architectures, compare the critical path, throughput, and latency of the pipelined and nonpipelined versions. d. Which architecture is better suited to pipelining, and how does the choice of a vectormerging adder affect this decision [M, None, 11.

4] Estimate the delay of a 16x16 Wallace tree multiplier with the final adder implemented using a Radix-4 tree. One FA has a delay of tp , a HA 2/3*tp and a CLA stage *tp . [E, None, 11.

5] The layout of shifters is dominated by the number of wires running through a cell. For both the barrel shifter and the logarithmic shifter, estimate the width of a shifter cell as a function of the maximum shift-width M and the metal pitch p. [E, None, 11.

7] Consider the circuit from Figure 0.7 . Modules A and B have a delay of 10 ns and 32 ns at 2.

5V, and switch 15 pF and 56 pF respectively. The register has a delay of 2 ns and switches 0.1 pF.

Adding a pipeline register allows for reduction of the supply voltage while maintaining throughput. How much power can be saved this way Delay with respect to V DD can be approximated from Figure 11-57. [E, None, 11.

7] Repeat Problem 16, using parallelism instead of pipelining. Assume that a 2to-1 multiplexer has a delay of 4 ns at 2.5 V and switches 0.

3 pF. Try parallelism levels of 2 and by 4. Which one is preferred .

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